High speed serial links use a serializer/deserializer (SERDES) in the transmitting and receiving integrated circuits. A transmitting SERDES transforms parallel data from a relatively low-speed clock domain into serialized data at a relatively high-speed clock rate. A receiving SERDES deserializes the serialized data back into parallel data. The high-speed clock is embedded with the transmitted serialized data. The receiving SERDES thus includes a clock recovery circuit to recover the embedded high-speed clock. But the clock recovery circuit presumes the existence of a valid received serialized signal. If the received signal has an insufficient signal amplitude such as from a low signal-to-noise ratio (SNR), unacceptable error rates will result. The amplitude of the received serialized signal must be sufficiently large to achieve low bit error rates. A sufficient signal amplitude enables a high signal-to-noise (SNR) ratio upon receipt and also assures open data eyes in the receiver inputs. Thus, it is conventional for high-speed serial links to include a loss-of-signal detector. The SERDES will not deserialize the received signal if the loss-of-signal detector indicates that the received signal is lost or invalid.
But accurate signal detection is a challenging task in high-speed serial links such as used for multi-giga-bit-per-second protocols. In particular, loss-of-signal detection needs to be independent of the transmitted data. In other words, events such as random data, consecutive identical data, or common mode voltage variation should not degrade the loss-of-signal detection quality. In addition, loss-of-signal detection should not degrade the return loss performance of the associated receiver input.
To attempt to satisfy these goals for loss-of-signal detection, traditional high-speed serial links have used a peak detection approach such as used in squelch circuits. A half-wave or full-wave rectifier rectifies the incoming data in one polarity and retains the peak signal amplitude of the rectified input signal using a low-pass filter such as a capacitor. A high-speed comparator compares the peak signal amplitude with a reference voltage to determine whether a loss-of-signal has occurred. The high-speed comparator typically requires hysteresis to avoid unwanted signal detection transitions. These traditional approaches to loss-of-signal detection suffer from data dependency, process and temperature variations, and other deleterious effects. Moreover, device leakage becomes a problem in the smaller process nodes.
An alternative to the peak detection approach involves the use of an analog multiplier cell to rectify the incoming data and add it to a reference voltage. A differential comparator detects a differential rectified output signal from the analog multiplier cell to determine whether a loss-of-signal had occurred. Dependency to the common mode voltage of the input data is a major problem for such an analog multiplier technique. In addition, the multiplier cells have a limited bandwidth and are dependent on the data rate. The signal detection accuracy for analog multiplier cell architectures is thus problematic.
Accordingly, there is a need in the art for improved loss-of-signal detectors for high-speed serial links.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.